Method and System for Storing Logical Data Blocks Into Flash-Blocks in Multiple Non-Volatile Memories Which Are Connected to At Least One Common Data I/0 Bus

ABSTRACT

For recording or replaying in real-time digital HDTV signals very fast memories are required. For storage of streaming HD video data NAND flash memory based systems can be used. However, NAND flash memories have a slow write access, and they have unmasked production defects. Write or read operations can be carried out on complete physical data blocks only, and defect data blocks must not be used by the file system. Logical file system blocks are used which are larger than the physical data blocks. According to the invention the error reporting mechanism of the NAND flash memories is exploited. The video data is not only written to the non-volatile flash memories, but is also written to corresponding buffer slots (LFSB) of a volatile SRAM or DRAM memory operating in parallel. The video data are kept in the vola- tile memory until the flash memory holding the respective data has reported that its program or write operation succeeded. Once this has taken place, the data within the volatile memory can be overwritten in order to save memory capacity. If the flash memory has reported an error, the respective block (FSBD) of data is marked bad and will not be overwritten until the end of the entire recorded take has been reached. At this time, the marked video data from the volatile memory are copied to spare flash-blocks within the flash memories.

The invention relates to a method and to a system for storing logicaldata blocks into flash-blocks in multiple non-volatile memories whichare connected to at least one common data I/O bus, whereby data fordefect flash-blocks are stored elsewhere.

BACKGROUND

For (professional) film and video recording or replaying in real-timedigital high bandwidth video signals, e.g. HDTV signals, digitalcinematography, very fast memories are required. For storage ofstreaming HD video data NAND flash memory based systems could be used.Flash memory devices are physically accessed in a page oriented mode,whereby one ‘page’ includes e.g. 1024 data words and related errorcorrection code (ecc).

NAND flash memories have two basic disadvantages:

-   -   the write access is rather slow;    -   they have unmasked production defects and acquire even more        defects during their lifetime. The required error handling is        under user responsibility.

Erase operations on a specific flash memory can be carried out oncertain-size data blocks only. These data blocks are denoted by the term“flash-block” in the following. A flash-block consists of e.g. 64 pages.Since a detection of defects in flash memory devices (e.g. NAND devices)takes place for instance during an erase operation, a defect in a pagemakes an entire flash-block unusable. Such defect flash-blocks must notbe used by the file system.

A known approach for tackling sporadic defects during operation is tointroduce redundancy, e.g. by a corresponding channel coding or by adata re-transmission.

INVENTION

For the recording of streaming video, the related file system mustprovide address values denoted “logical block numbers” of unused storagespace under real-time conditions, and it must take care of notaddressing defect memory blocks. In a high-definition video recordingsystem, due to the slow write access, a high number of interleaved andparallel flash memory devices must be employed. This means that severalflash devices are to be accessed in parallel and all devices on the samebus are to be accessed in subsequent order to sustain the requiredstreaming bandwidth.

However, the above-mentioned approaches for introducing redundancy havethe disadvantage of requiring additional bandwidth for the storagedevices. But in a flash memory based streaming video recording system,adding bandwidth to the flash devices is the most critical and costlyresource at all because it would lead to demand for additionalparallelism, i.e. additional system size, power consumption and cost.

Access to NAND flash memories can take place using a 20 MHz bus clock.Most real-time critical is the write operation. After an entire page hasbeen entered into a memory device, a ‘program’ command (i.e. a writecommand) is issued which initiates copying of data from a flash memoryinternal page register to the actual flash memory cells. Such pageprogram operation requires 700 μs in the worst case. The page registermust not be accessed during this time period. However, data transfer tothe page registers of other flash memories on the same bus may takeplace during this time. Within such 700 μs time period, when using businterleaving, data can be transferred to 10-15 other flash memories thatare connected to the same bus.

Typical NAND flash memories provide a status information after eachprogram or write operation for a page, whether or not the operationsucceeded, i.e. whether or not a defect occurred.

A problem to be solved by the invention is to provide for a flashmemory-based storage system, in case of writing error due to a memorydata block defect, a corresponding error handling. This problem issolved by the method disclosed in claim 1. A storage system thatutilises this method is disclosed in claim 2.

According to the invention the above error reporting mechanism isexploited. The video data is not only written to the non-volatile flashmemories, but is also written to volatile one or more SRAM or DRAMmemories operating in parallel with the flash memories. The parallelaccess to SRAM or DRAM is uncritical because such memory devices offer amore than sufficient bandwidth as compared to that of flash memories.The video data are kept in the volatile memory until the flash memoriesholding the respective data have reported that their program or writeoperation succeeded. Once this has taken place, the data within thevolatile memory can be overwritten in order to save memory capacity. Ifa flash memory has reported an error, the respective logical block ofdata is marked ‘bad’ and will not be overwritten until the end of theentire recorded take has been reached. At this time, the busses to theflash memories are idle, and the entire bandwidth can be employed tofirst copy the marked data of the flash-block from the respective flashmemory (i.e. the flash memory that had reported a defect) to spareflash-block or blocks within that flash memory, and then copy thecorresponding erroneous page or pages from the SRAM or DRAM memory tothe corresponding page or pages in the corresponding spare flash-blockor blocks.

Advantageously, such parallel storage of streaming data into volatileRAM (SRAM or DRAM) does not waste bandwidth.

Preferably, the logical file system blocks and the physical memoryblocks do not have the same size. A logical file system block is thecombination of one flash-block from all flash memory devices used in theentire storage system. Such logical file system block becomes thesmallest addressable system entity when using the file system tables.The file system uses separated tables for bad block remap and fileallocation (FAT). The bad block mapping is kept on single flash-blocklevel using ‘block indirection tables’, one block indirection table perflash memory device.

Only the writing into the flash memories is carried out on a page basis,whereby the same page number N in all flash memories forms a logicalpage N of the storage system.

The invention facilitates a fully transparent masking of flash memorydefects acquired during recording without need for additional bandwidthto the flash memories. This saves system size, power consumption andcosts. Additional SRAM/DRAM must be integrated into the storage system,but such additional memory is likely already present for other reasons.

In principle, the inventive method is suited for storing logical datablocks in a storage system that includes multiple non-volatile memorieswhich are connected to at least one common data I/O bus, wherein eachone of said non-volatile memories can be physically accessed by memorypages which each include multiple data words and each one of saidnon-volatile memories can be logically accessed by flash-blocks whicheach include multiple ones of said memory pages, said method includingthe steps:

-   -   storing page data blocks into flash-blocks of multiple        non-volatile memories and in parallel into corresponding buffer        slots in volatile memory means, in a circular buffer slot access        sequence, whereby the respectively used storage capacity of said        volatile memory means is smaller than the storage capacity of        said non-volatile memories and whereby, after the last free        buffer slot has been written, said sequence again starts with        overwriting the first buffer slot,

and whereby, if one or more of said non-volatile memories signal that,when recording a current page data block an error has occurred in thatpage data block, the corres-ponding current buffer slot in said volatilememory means—or a related table entry—is marked correspondingly and inthe following turn or turns of said sequence said marked buffer slot orslots are skipped such that the data stored therein are kept unchanged;

-   -   after a take has been recorded into said non-volatile memories,        copying flash-block data of said volatile memory means that        contain erroneous page data into free flash-blocks in the        corresponding flash memories, and checking which buffer slots in        said volatile memory means or which related table entries are        marked and copying corresponding page data block data from said        marked buffer slots of said volatile memory means into the        corresponding pages of said free flash-blocks in said        non-volatile memories.

In principle the inventive storage system stores logical data blocks inmultiple non-volatile memories which are connected to at least onecommon data I/O bus, wherein each one of said non-volatile memories canbe physically accessed by memory pages which each include multiple datawords and each one of said non-volatile memories can be logicallyaccessed by flash-blocks which each include multiple ones of said memorypages, said storage system including:

-   -   multiple non-volatile memories;    -   volatile memory means;    -   means for storing page data blocks into flash-blocks of multiple        non-volatile memories and in parallel into corresponding buffer        slots in volatile memory means, in a circular buffer slot access        sequence, whereby the respectively used storage capacity of said        volatile memory means is smaller than the storage capacity of        said non-volatile memories and whereby, after the last free        buffer slot has been written, said sequence again starts with        overwriting the first buffer slot,

and wherein, if one or more of said non-volatile memories signal that,when recording a current page data block an error has occurred in thatpage data block, the corres-ponding current buffer slot in said volatilememory means—or a related table entry—is marked correspondingly and inthe following turn or turns of said sequence said marked buffer slot orslots are skipped such that the data stored therein are kept unchanged;

-   -   means which, after a take has been recorded into said        non-volatile memories, copy flash-block data of said volatile        memory means that contain erroneous page data into free        flash-blocks in the corresponding flash memories, and check        which buffer slots in said volatile memory means or which        related table entries are marked, and copy corresponding page        data block data from said marked buffer slots of said volatile        memory means into the corresponding pages of said free        flash-blocks in said non-volatile memories.

Advantageous additional embodiments of the invention are disclosed inthe respective dependent claims.

DRAWINGS

Exemplary embodiments of the invention are described with reference tothe accompanying drawings, which show in:

FIG. 1 block diagram of the inventive memory system;

FIG. 2 principle of parallel catching of data to be recorded, andsubsequent copy to spare flash-blocks;

FIG. 3 principle of SRAM memory organisation and address sequence.

EXEMPLARY EMBODIMENTS

The following NAND flash memories can be used: Samsung K9K2G16UOM-YCB000(2 Gbit, 16 bit oriented), K9W4G08U0M-YCB000 (4 Gbit, 8 bit oriented),Toshiba TH58NVG2S3BFT00 (4 Gbit, 8 bit oriented) and MICRON MT29G08AAxxx(2 Gbit, 8 bit oriented), MT29G16AAxxx (2 Gbit, 16 bit oriented).

A bus structure for the connection of the memory devices is shown inFIG. 1. Each bus BS0, BS1, . . ., BSN-1 features a number of 28 flashmemories D0, D1, D2, . . ., DN-2, DN-1, whereby 8 busses are operatingin parallel, which equals 224 flash memory devices in total. Each busBS0, BS1, . . ., BSN-1 can write to, or read from, the memory devices16-bit words IO0..15 and operating at 20 MHz. These data inputs/outputsare used to input command, address and data, and to output data duringread operations. The I/O pins float to high-s when the chip isdeselected or when the outputs are disabled.

RY/ BY is a ready/busy output indicating the status of the deviceoperation. When low, it indicates that a program, erase or random readoperation is in process and returns to high state upon completion. It isan open drain output and does not float to high-s condition when thechip is deselected or when outputs are disabled.

This status of the device operation and/or data from IO0..15 can be usedto determine whether or not a write defect has occurred.

RE is a read enable signal whereas WE is a write enable signal. The readenable input is a serial data-out control and, when active, drives thedata onto the I/O bus. Data is valid after the falling edge of readenable which also increments an internal column address counter by one.The write enable input controls writes to the I/O port. Commands,address and data are latched on the rising edge of the write enablepulse.

The command latch enable input CLE controls the activating path forcommands sent to a command register. When active high, commands arelatched into the command register through the I/O ports on the risingedge of the write enable signal. The address latch enable input ALEcontrols the activating path for address to the internal addressregisters. Addresses are latched on the rising edge of the write enablesignal with ALE high.

CE 0, CE 1, CE 2, . . ., CEN-2 and CEN-1 denote a chip enable input andare used for device selection control. When the device is in the busystate, CE high is ignored and the device does not return to a standbymode in a program or erase operation.

A memory or micro controller unit MCTRL controls all flash memorydevices using the above-listed signals. Controller MCTRL receives videodata VD for recording, or outputs recorded video data VD for replay. Anadditional memory means RAM (SRAM and/or DRAM) is connected tocontroller unit MCTRL and stores the current video data, the requiredfile system and defect block remap tables.

When writing, each flash memory is accessed page by page in eachflash-block, and flash-block by flash-block. The bank of memories isaccessed per page, memory by memory.

Preferably SRAM (e.g. 2*2 GBit) is employed in order to keep theinterfacing as simple as possible. The SRAM is organised as 64-bit busat 80 MHz—hence providing identical bandwidth. All buffer managementtakes place on logic file system block level, whereby the logical blocksare much larger than a flash-block. The flash memories report theirerror status after each write operation on page level.

The SRAM can hold up to 16 logic file system blocks. As a consequence,the system can mask at least 16 defects, or even more if multipledefects fall into the same logic file system block. When considering theerror statistics of flash memory devices, the resulting mean timebetween failures of the inventive storage system advantageously is farbeyond user concern. The same SRAM can also be used to hold theabove-mentioned file system and error handling tables.

FIG. 2 shows in its top part the parallel writing of (page) video dataVD to be recorded into the flash memories and into the SRAM. In itsbottom part FIG. 2 depicts the copying of (page) video data from theSRAM to spare flash-blocks in case a write error occurred during therecoding into the flash memories. That copy operation is performedimmediately after a corresponding take recording operation has beenfinished.

The principle of the SRAM memory organisation in FIG. 3 shows multiplebuffer slots each containing a logical page data block LFSB. Therespective storage area of the SRAM is filled slot by slot with theincoming video data, which processing is depicted by the current bufferaddress sequence CBAS. After the last free buffer slot has been written,the sequence again starts with overwriting the first buffer slot. If theflash memory bank signals that, when recording a current logical pagedata block, an error has occurred in a flash-block the correspondingcurrent slot in the SRAM (or a respective table) is markedcorrespondingly. The grey or hatched slots mark logical page data blocksFSBD containing data corresponding to defect flash-blocks of the relatedflash memories. In the next turn the SRAM slot access sequence will skipthat marked buffer slot (and all other marked slots) such that the datastored therein are kept unchanged.

After a take has been recorded into the flash memory bank D0, D1, D2, .. ., DN-2, DN-1, the file allocation and bad block remap tables are usedto check which flash blocks in the flash memories can store furthervideo data. The video data stored in the flash-blocks containing one ormore page errors are thereafter copied into the corresponding free(non-defect) flash-blocks in the flash memories. Then, the requirederror-free page data intermediately stored in the SRAM from the markedslots of the SRAM are copied into the corresponding erroneous pages inthe flash-block data that have just been stored before in the freeflash-blocks in the flash memories.

According to the logical block layout described above, a logical filesystem block contains 28 Mbytes, whereas typical state-of-the-art filesystems feature block sizes in Kbytes range. The file system containsonly e.g. 2048 logical blocks. The maximum number of files that may bestored on the storage system is 255 plus one extra file representing anempty logical block list. However, a typical quantity is <20. In a worstcase this would mean that partially filled logical blocks at the end ofeach file may lead to unused space amounting to 12.5% of the totalstorage capacity, but in practise a value of <2% is more realistic.

When reading video data from the storage system the replacementflash-block data are read from the flash memories, instead of theerroneous flash-blocks, controlled by the logical file system.

1-8. (canceled)
 9. Method for storing logical data blocks in a storagesystem that includes multiple non-volatile memories which are connectedto at least one common data I/O bus, wherein each one of saidnon-volatile memories can be physically accessed by memory pages whicheach include multiple data words and each one of said non-volatilememories can be logically accessed by flash-blocks which each includemultiple ones of said memory pages, said method comprising the steps:storing page data blocks into flash-blocks of multiple non-volatilememories and in parallel into corresponding buffer slots in volatilememory means, in a circular buffer slot access sequence, whereby therespectively used storage capacity of said volatile memory means issmaller than the storage capacity of said non-volatile memories andwhereby, after the last free buffer slot has been written, said sequenceagain starts with overwriting the first buffer slot, and whereby, if oneor more of said non-volatile memories signal that, when recording acurrent page data block an error has occurred in that page data block,the corresponding current buffer slot in said volatile memory means or arelated table entry is marked correspondingly and in the following turnor turns of said sequence said marked buffer slot or slots are skippedsuch that the data stored therein are kept unchanged; after a take hasbeen recorded into said non-volatile memories, copying flash-block dataof said volatile memory means that contain erroneous page data into freeflash-blocks in the corresponding flash memories, and checking whichbuffer slots in said volatile memory means or which related tableentries are marked and copying corresponding page data block data fromsaid marked buffer slots of said volatile memory means into thecorresponding pages of said free flash-blocks in said non-volatilememories.
 10. Method according to claim 9, wherein said non-volatilememories are NAND flash memories.
 11. Method according to claim 9,wherein said storage system stores or replays streaming video data inreal-time.
 12. Method according to claim 9, wherein access to saidnon-volatile memories is performed in circular subsequent order. 13.Method according to claim 9 wherein, in order to mask defects in storagecells of said NAND flash memories, to each one of said NAND flashmemories a block indirection table is assigned that maps logical datablock address values to physical address values related to non-defectflash-blocks.
 14. Method according to claim 13, wherein said storagesystem includes micro or memory control means which control said atleast one common data I/O bus and to which control means RAM memorymeans are connected which store said block indirection tables. 15.Method according to claim 9, wherein said RAM memory means is an SRAMmemory.
 16. Storage system for storing logical data blocks in multiplenon-volatile memories which are connected to at least one common dataI/O bus, wherein each one of said non-volatile memories can bephysically accessed by memory pages which each include multiple datawords and each one of said non-volatile memories can be logicallyaccessed by flash-blocks which each include multiple ones of said memorypages, said storage system comprising: multiple non-volatile memories;volatile memory means); means for storing page data blocks intoflash-blocks of multiple non-volatile memories and in parallel intocorresponding buffer slots in volatile memory means, in a circularbuffer slot access sequence, whereby the respectively used storagecapacity of said volatile memory means is smaller than the storagecapacity of said non-volatile memories and whereby, after the last freebuffer slot has been written, said sequence again starts withoverwriting the first buffer slot, and wherein, if one or more of saidnon-volatile memories signal that, when recording a current page datablock an error has occurred in that page data block, the correspondingcurrent buffer slot in said volatile memory means or a related tableentry is marked correspondingly and in the following turn or turns ofsaid sequence said marked buffer slot or slots are skipped such that thedata stored therein are kept unchanged; meansmeans which, after a takehas been recorded into said non-volatile memories, copy flash-block dataof said volatile memory means that contain erroneous page data into freeflash-blocks in the corresponding flash memories, and check which bufferslots in said volatile memory means or which related table entries aremarked, and copy corresponding page data block data from said markedbuffer slots of said volatile memory means into the corresponding pagesof said free flash-blocks in said non-volatile memories.
 17. Systemaccording to claim 16, wherein said non-volatile memories are NAND flashmemories.
 18. System according to claim 16, wherein said storage systemstores or replays streaming video data in real-time.
 19. Systemaccording to claim 16, wherein access to said non-volatile memories isperformed in circular subsequent order.
 20. System according to 16,wherein, in order to mask defects in storage cells of said NAND flashmemories to physical address values related to non-defect flash-blocks.21. System according to claim 20, wherein said storage system includesmicro or memory control means which control said at least one commondata I/O bus and to which control means RAM memory means are connectedwhich store said block indirection tables.
 22. System according to claim16, wherein said RAM memory means is an SRAM memory.